As a technique for realizing a high-speed and high-performance LSI, the reduction of dielectric constant of an interlayer insulator and the adoption of Cu wiring formed by using the damascene method have become more and more indispensable. Especially, the reduction of dielectric constant of an interlayer insulator is a quite important technique because it can reduce not only the capacity between wirings but also the power consumption in the LSI.
As the damascene method, the single damascene method in which plugs are embedded in via holes and then Cu wiring is formed in wiring trenches and the dual damascene method in which the Cu wiring is formed simultaneously in the via holes and the wiring trenches are known. However, from the viewpoint of the reduction in the number of process steps, it is expected that the dual damascene method will become the mainstream.
An example of the process of forming the Cu wiring by the use of the dual damascene method will be described. First, an interlayer insulator is formed on a lower wiring and then an insulator for a hard mask is deposited on the interlayer insulator. Subsequently, the dry etching is performed with using a photoresist film as a mask so as to form the via holes in the insulator for a hard mask and the interlayer insulator. Next, after removing the photoresist film, the dry etching is performed halfway into the interlayer insulator with using the insulator for a hard mask as a mask, thereby forming wiring trenches. As described above, since the etching of the interlayer insulator is stopped halfway in the process of forming the wiring trenches, an insulator having an etching selectivity to the interlayer insulator higher than that of a photoresist film is used as the mask in this etching. Thereafter, the Cu film is embedded in the via holes and the wiring trenches by sputtering or plating, and then, the Cu film outside the wiring trenches is removed by the chemical mechanical polishing. In this manner, the Cu wiring is formed.
Japanese Patent Application Laid-Open No. 2003-168738 discloses the case where an SiOC insulator having a dielectric constant lower than that of a silicon oxide film is used as an interlayer insulator used when forming the Cu wiring by the damascene method, wherein a silicon nitride film, a silicon carbide (SiC) film, and an SiCN (silicon carbonitride) film are shown as an insulator for a hard mask.
Although it does not relate to the damascene method, Japanese Patent Application Laid-Open No. 2000-31899 discloses a technique for patterning the metal wiring of fine lines and spaces, in which a hard mask layer composed of a metal oxide film and a photoresist film deposited thereon are used as masks. It is said that tantalum oxide, alumina, and titanium dioxide are preferably used as the metal oxide.